A formal approach to the mapping of tasks on an heterogenous multicore, energy-aware architecture

International audienceThe search for optimal mapping of application (tasks) onto processor architecture (resources) is always an acute issue, as new types of heterogeneous multicore architectures are being proposed constantly. The physical allocation and temporal scheduling can be attempted at a number of levels, from abstract mathematical models and operational research solvers, to practical simulation and run-time emulation. This work belongs to the first category. As often in the embedded domain we take as optimality metrics a combination of power consumption (to be minimized) and performance (to be maintained). One specificity is that we consider a dedicated architecture, namely the big.LITTLE ARM-based platform style that is found in recent Android smartphones. So now tasks can be executed either on fast, energy-costly cores, or slower energy-sober ones. The problem is even more complex since each processor may switch its running frequency, which is a natural trade-off between performance and power consumption. We consider also energy bonus when a full block (big or LITTLE) can be powered down. This dictates in the end a specific set of requirements and constraints, expressed with equations and inequations of a certain size, which must be fed to an appropriate solver (SMT solver in our case). Our original aim was (and still is) to consider whether these techniques would scale up in this case. We conducted experiments on several examples, and we describe more thoroughly a task graph application based on the tiled Cholesky decomposition algorithm, for its relevant size complexity. We comment on our findings and the modeling issues involved

Multicore SMT scheduling of periodic task systems with energy minimization

International audienceEnergy budget is an intrinsic limitation of mobile electronic appliances such as smartphones or other connected objects. Energy saving is made to compete in modern design against performance optimization. Energy saving mechanisms are usually available (such as power or clock gating, frequency/voltage scaling), but methods to assess their efficiency operate at diverse levels. Either very high, with Excel-like formulas expressing cost functions in systems where applicative dynamic aspects are scarcely present, or already rather low with SystemC transaction-level simulation models in which dynamic abstractions of both actual applicative code and underlying Operating System and instruction-set architecture are needed. In the present paper we describe an intermediate level practical technique for exploiting power/performance ratio information with mathematical solving methods, such as Sat Modulo Theories (SMT) and Constraint Programming. The goal is to get estimation results and optimization proposals at the medium intermediate range, where application use cases have dynamic behaviors, but at a level much coarser than instruction-level code or even algorithmic function block. We present modeling and benchmark results illustrating our approach on a simple big.LITTLE-type architecture

Application Architecture Adequacy through an FFT case study

International audienceApplication Architecture Adequacy (AAA) aims at tuning an application to a given hardware architecture. However it is still a difficult and error prone activity. As like as in Hardware/Software co-design, it requires a model of both the application and the architecture. With the new highly-parallel architectures, AAA should also allow a fast exploration of different software mapping granularity in order to leverage better the hardware resources without sacrifying too much productivity. The main contribution of this paper is to extract from a case study a methodology based on dataflow modeling to make the software both faster to develop and suited to the target. Then we show how this methodology can solve some of these issues

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling

International audienceRecent papers have reported on successful application of constraint solving techniques to off-line real-time scheduling problems, with realistic size and complexity. Success allegedly came for two reasons: major recent advances in solvers efficiency and use of optimized, problem-specific constraint representations. Our current objective is to assess further the range of applicability and the scalability of such constraint solving techniques based on a more general and agnostic evaluation campaign. For this, we have considered a large number of synthetic scheduling problems and a few real-life ones, and attempted to solve them using 3 state-of-the-art solvers, namely CPLEX, Yices2, and MiniZinc/G12. Our findings were that, for all problems considered, constraint solving does scale to a certain limit, then diverges rapidly. This limit greatly depends on the specificity of the scheduling problem type. All experimental data (synthetic task systems, SMT/ILP models) are provided so as to allow experimental reproducibility

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling

Recent papers have reported on successful application of constraint solving techniques to off-line real-time scheduling problems, with realistic size and complexity. Success allegedly came for two reasons: major recent advances in solvers efficiency and use of optimized, problem-specific constraint representations. Our current objective is to assess further the range of applicability and the scalability of such constraint solving techniques based on a more general and agnostic evaluation campaign. For this, we have considered a large number of synthetic scheduling problems and a few real-life ones, and attempted to solve them using 3 state-of-the-art solvers, namely CPLEX, Yices2, and MiniZinc/G12. Our findings were that, for all problems considered, constraint solving does scale to a certain limit, then diverges rapidly. This limit greatly depends on the specificity of the scheduling problem type. All experimental data (synthetic task systems, SMT/ILP models) are provided so as to allow experimental reproducibility

Explicit Control of Dataflow Graphs with MARTE/CCSL

International audienceProcess Networks are a means to describe streaming embedded applications. They rely on explicit representation of task concurrency, pipeline and data-flow. Originally, Data-Flow Process Network (DFPN) representations are independent from any execution platform support model. Such independence is actually what allows looking next for adequate mappings. Mapping deals with scheduling and distribution of computation tasks onto processing resources, but also distribution of communications to interconnects and memory resources. This design approach requires a level of description of execution platforms that is both accurate and simple. Recent platforms are composed of repeated elements with global interconnection (GPU, MPPA). A parametric description could help achieving both requirements. Then, we argue that a model-driven engineering approach may allow to unfold and expand an original DFPN model, in our case a so-called Synchronous DataFlow graph (SDF) into a model such that: a) the original description is a quotient refolding of the expanded one, and b) the mapping to a platform model is a grouping of tasks according to their resource allocation. Then, given such unfolding, we consider how to express the allocation and the real-time constraints. We do this by capturing the entire system in CCSL (Clock Constraint Specification Language). CCSL allows to capture linear but also synchronous constraints. Lastly, the system can be checked for the existence of a schedule satisfying all the constraints using a state space exploration technique. The approach is validated on a typical embedded system application allocated on a multi-core platform

Multicore SMT scheduling of periodic task systems with energy minimization

International audienceEnergy budget is an intrinsic limitation of mobile electronic appliances such as smartphones or other connected objects. Energy saving is made to compete in modern design against performance optimization. Energy saving mechanisms are usually available (such as power or clock gating, frequency/voltage scaling), but methods to assess their efficiency operate at diverse levels. Either very high, with Excel-like formulas expressing cost functions in systems where applicative dynamic aspects are scarcely present, or already rather low with SystemC transaction-level simulation models in which dynamic abstractions of both actual applicative code and underlying Operating System and instruction-set architecture are needed. In the present paper we describe an intermediate level practical technique for exploiting power/performance ratio information with mathematical solving methods, such as Sat Modulo Theories (SMT) and Constraint Programming. The goal is to get estimation results and optimization proposals at the medium intermediate range, where application use cases have dynamic behaviors, but at a level much coarser than instruction-level code or even algorithmic function block. We present modeling and benchmark results illustrating our approach on a simple big.LITTLE-type architecture

Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core Architectures

International audienceThe advent of chip-level parallel architectures prompted a renewal of interest into dataflow process networks. The trend is to model an application independently from the architecture, then the model is morphed to best fit the target architecture. One downplayed aspect is the mapping of communications through the on-chip topology. The cost of such communications is often prevalent with regard to computations.This article establishes a dataflow process network called K-periodically Routed Graph (KRG), which serves the role of representing the various routing decisions during the transformation of a genuine application into a architecture-aware version for this application